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From Scottie · July 31, 2026
See SemiAnalysis in a Scottie brief
Scottie read SemiAnalysis, Vik's Newsletter, and The Diligence Stack for a reader with the priorities shown below. Start with the rundown, open the full brief, or check every issue behind it.
3sources
6issues read
6stories included
2 of 2 SemiAnalysis issues included
What shaped this brief
Reader priorities
A technical investor or infrastructure leader following AI chips, compute systems, model economics, and semiconductor competition.
These are illustrative priorities, not a customer’s data.
Sources in this brief
- SemiAnalysisThe publication this guide is about
- Vik's NewsletterAdds specialist analysis of power delivery, memory, optics, and data-center components.
- The Diligence StackAdds hyperscaler capacity, storage, and infrastructure investment analysis.
Scottie
Scottie example brief
July 31, 2026 · Executive brief
01 / The rundown
- Hyperscalers are adopting behind-the-meter power and modular builds to bypass severe grid delays that will bottleneck datacenter capacity through 2030.
- AMD is making silicon strides with its 2nm MI455X chip, but internal GPU cluster shortages threaten its software progress against Nvidia.
- AI compute intensity is shifting semiconductor economics, driving memory revenues toward $850B by 2027 while exposing high-bandwidth memory design limits.
Read the complete brief 6 stories · 3 action items
02 / The briefing
01 / main
AMD advances 2nm silicon but faces internal software cluster crunches
The takeaway: AMD is stepping up hardware competition with its 2nm MI455X chip, securing large commitments from Anthropic and OpenAI. However, severe internal GPU cluster shortages are delaying automated CI testing and threatening software progress against CUDA.
Concrete details
- MI455X features 3,470mm² of logic silicon using TSMC 2nm tiles and CoWoS-L 5.5x reticle packaging.
- Helios racks require over 550 Broadcom ethernet retimers per rack, with up to 85% of backplane retimed.
Why it matters for this reader: As an investor tracking semiconductor competition, monitoring AMD's internal test capacity is vital to evaluating whether their ROCm software stack can truly challenge Nvidia's dominance.
Original sourcesSemiAnalysis
02 / main
Hyperscalers adopt behind-the-meter power to bypass grid delays
The takeaway: Hyperscalers are turning to behind-the-meter generation to bring datacenter shells online faster without waiting for grid hookups. Lower power spikes from inference workloads make onsite power generation far easier to manage.
Concrete details
- Interactive inference creates a 9% power spike compared to a 37.5% maximum jump for training workloads.
- Bloom Energy Q2 revenue reached $1.065 billion, up 165.5% year-over-year with a 33.4% gross margin.
Why it matters for this reader: For your compute economics models, onsite generation shortens time-to-revenue by side-stepping utility delays, altering how cloud operators deploy capital.
Original sourcesThe Diligence Stack
03 / main
Grid bottlenecks force hyperscalers and chipmakers to lease physical shells
The takeaway: Power constraints will limit datacenter builds through 2030 as grid studies take up to 12 months. To secure fast capacity, both hyperscalers and chipmakers like Nvidia and AMD are directly leasing third-party physical infrastructure.
Concrete details
- Backlog-to-capex ratios for top cloud operators fell from 44% in 2024 to about 37% in 2026.
- Core Scientific has 437 MW billing out of 1.1 GW leased, backed by direct AMD lease deals.
Why it matters for this reader: Understanding who controls the physical shell versus the compute layer helps you evaluate margin preservation across hyperscalers and specialized data center operators.
Original sourcesThe Diligence Stack
04 / main
Non-accelerator hardware costs skyrocket as semiconductor ASPs triple by 2028
The takeaway: Past forecasts drastically underestimated system-level AI hardware demand beyond GPUs. Average semiconductor selling prices are set to nearly triple by 2028, driving massive revenue growth across packaging, memory, and networking.
Concrete details
- Blended semiconductor average selling prices are projected to rise from $0.75 to over $2.10 by 2028.
- Combined DRAM and NAND revenue is modeled to reach $800–$850 billion in 2027.
Why it matters for this reader: If you are evaluating compute supply chain value, hardware component scaling outside the main accelerator represents the primary driver of capital expansion.
Original sourcesThe Diligence Stack
05 / main
Modular construction cuts datacenter build times by nine months
The takeaway: Operators are deploying prefabricated, modular datacenters to beat mounting trade labor shortages. Offsite assembly shortens construction timelines significantly while helping vendors expand their revenue content per megawatt.
Concrete details
- Modular builds compress construction timelines by 36%—saving 7 to 9 months—and cut capex by 8% per MW.
- Modular datacenter penetration is projected to exceed 30% of total live capacity by late 2028.
Why it matters for this reader: Datacenter deployment speed directly drives revenue recognition; tracking modular adoption reveals which infrastructure providers can bypass skilled labor bottlenecks.
Original sourcesSemiAnalysis
06 / main
High-bandwidth memory faces physical design limits despite high supplier margins
The takeaway: Industry leaders acknowledge that HBM has severe structural flaws, including three times lower die bit-density than standard DRAM and intense thermal issues. However, capacity constraints will keep memory margins high for years.
Concrete details
- HBM requires three times more wafers than standard DRAM for equivalent memory capacity due to TSV area.
- Memory suppliers maintain near 90% gross margins amid persistent supply shortages expected to last 2 to 3 years.
Why it matters for this reader: As you model accelerator unit economics, tracking memory architecture shifts beyond HBM4 is essential to predicting future system cost structures.
Original sourcesVik's Newsletter
Action items
- Audit portfolio exposure to non-accelerator supply chain bottlenecks, focusing on memory ASP expansion and advanced packaging capacity.
- Review datacenter power strategies to evaluate behind-the-meter generation models and prefabricated modular construction partners.
- Track AMD software release benchmarks through October to verify whether internal compute shortages delay ROCm and vLLM parity.
See every issue behind this brief
Behind-the-Meter AI Infrastructure Buildout
- The Behind-the-Meter AI BuildoutThe Diligence Stack · Included
Hyperscaler Capacity Partner Hierarchy and Power Constraints
- The Hyperscaler Capacity Partner HierarchyThe Diligence Stack · Included
AMD's Progress Against Nvidia's CUDA Moat
- Can AMD break the CUDA Moat? AMD Advancing AI 2026SemiAnalysis · Included
Underestimating Scaling Speed for Accelerator Support Systems
- In 2023-2024 We Weren't Bullish EnoughThe Diligence Stack · Included
Modular Construction Methods in Datacenter Buildouts
- The Wild Wild West Of LEGO DatacentersSemiAnalysis · Included
Executive Debate on HBM Memory Bottlenecks
- HBM is the Ugly Baby: What Now?Vik's Newsletter · Included
About SemiAnalysis
Should you add SemiAnalysis to Scottie?
Understand the hardware, cost, and supply constraints behind frontier AI systems.[1][2][3]
Who it’s for
A technical investor or infrastructure leader following AI chips, compute systems, model economics, and semiconductor competition.[1][2]
What you’ll find in it
The issues linked below include “Claude Code is the Inflection Point”, “Can AMD break the CUDA Moat? AMD Advancing AI 2026”, and “Vera Rubin NVL72 vs GB200 NVL72? Inference TCO & Architecture Analysis”. Open them to judge the publication in its own words.
- Byline
- Dylan Patel[1]
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Scottie read 2 SemiAnalysis items and included 2 for the brief. The sources covered different things, so Scottie kept their stories separate instead of forcing a connection.
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